FIG. 15 is a diagram showing an example of a typical configuration of a conventional controller driver 100 (for example, see Non-Patent Document 1 below). Referring to FIG. 15, the controller driver 100 (display control driving apparatus) is arranged between an image rendering device 20, such as CPU (central processing unit), as an upper layer device, and a display unit 30, for receiving image data for display from the image rendering device 20 to control the display thereof on the display unit 30, and includes a display memory 121 for storing image data for at least one frame (termed a frame memory), a latch circuit 122, a data line drive circuit 123, a memory control circuit 124, a timing control circuit 125 and a grayscale voltage generating circuit 126. Meanwhile, the controller driver, shown in FIG. 15, is formed as e.g. a semiconductor device (IC).
In the controller driver 100, the memory control circuit 124 receives image data (k bits per pixel) from the image rendering device 20 to write image data (H bits per pixel in the horizontal direction and V pixels in the vertical direction, with each pixel being of k bits), in the display memory 121.
The timing control circuit 125 outputs a timing control signal to the memory control circuit 124, while supplying a latch signal, a gate start pulse signal and a strobe signal STB to the latch circuit 122, a gate line drive circuit 31 and to the data line drive circuit 123, respectively.
The latch circuit 122 latches data for one line (H pixels×k bits), read and output from the display memory 121, responsive to the latch signal from the timing control circuit 125, to send the so latched data to the data line drive circuit 123.
The data line drive circuit 123 receives a grayscale voltage output (analog voltage) from the grayscale voltage generating circuit 126, and receives a digital data signal (k bits) from the latch circuit 122 to drive the data line of the display unit 30 with a grayscale voltage signal corresponding to the data signal. The data line drive circuit 123 is activated by the strobe signal STB from the timing control circuit 125. A pixel switch, not shown, connected to the gate line selected and activated by the gate line drive circuit 31 is turned on, and a grayscale voltage signal from the data line, the pixel switch is connected to, is applied to the display element for pixel (pixel electrodes in the case of liquid crystal elements), whereby pixels of one horizontal line are displayed. By the same sequel of operations, pixel data of pixels for one horizontal line, output in succession from the display memory 121, are latched by the latch circuit 122. A grayscale voltage signal is output from the data line drive circuit 123 to the display unit 30, and the horizontal line, as selected by the gate line drive circuit 31, is sequentially displayed to display V lines forming one frame. The gate line drive circuit 31 is responsive to a gate start pulse signal to advance the selected line by one to activate the associated gate line. The gate line drive circuit 31 is composed e.g. by a shift register which receives a gate start pulse signal, as a shift clock, for example, to shift a gate line to be activated sequentially.
In the controller driver 100, shown in FIG. 15, the latch circuit 122 includes H latch circuits arranged in parallel, latching image data of H pixels, equivalent to a horizontal line. It is noted that the image data per pixel is of k bits, and that each of the latch circuits latches simultaneously k-bit parallel data with the received latch signal. In similar manner, the data line drive circuit 123 includes H data line drive circuits arranged in parallel for driving H data lines. In FIG. 15, for the sake of simplicity of illustration, pixel data for a pixel are displayed in gray scale made up of a luminance signal. In case RGB data are provided as data for one pixel, the image data for one pixel is e.g. 3×k bits.
FIG. 16 shows an example of the timing operation of a display apparatus shown in FIG. 15. In FIG. 16, CLK denotes a clock signal supplied to the controller driver 100, an Address is an access address of the display memory 121 and k-bit input image data [k−1: 0] is image data of k bits in width, supplied from the image rendering device 20 to the controller driver 100. Meanwhile, [k−1: 0] in the input image data [k−1: 0] means parallel bit data from bit 0 to the number [k−1] bit, with the bit width of k bits. A display memory control signal is output from a memory control circuit 124 to a display memory 121. The latch signal is a signal output from the timing control circuit 125 to the latch circuit 122. The strobe signal STB is a signal supplied from the timing control circuit 125 to the data line drive circuit 123.
Referring to FIG. 16, write image data are sequentially written in associated addresses of the display memory 121, every clock cycle, responsive to a display memory WRITE signal (pulse signal), output every cycle of the clock signal CLK, under control by the memory control circuit 124. That is, as input image data for pixels of one horizontal line, input image data for (n+1) pixels are sequentially entered in association with (n+1) (=H) addresses, with the address y along the column direction of 0 and the addresses x along the row direction of from 0 to n in the display memory 121. The memory control circuit 124 outputs a display memory WRITE signal (pulse signal) every clock cycle and, responsive to the a display memory WRITE signal, write image data are sequentially written in the display memory 121, in terms of a pixel as a unit. In the case of FIG. 16, write image data items D0, D1, D2, D3, . . . , Dn−1, and Dn are sequentially written in the display memory 121, responsive to the display memory WRITE signal, activated every clock cycle. The image data, stored in the display memory 121, are read from the display memory 121 every line (every H pixels), for example, and image data of the pixels of one horizontal line, output in parallel, are latched by H latch circuits of the latch circuit 122, responsive to a latch signal output from the timing control circuit 125, such that the grayscale voltage matched to the image data is output, by the data line drive circuit, activated responsive to the strobe signal STB, to the data line of the display unit 30, responsive to the data line drive circuit 123, activated responsive to the strobe signal STB.
Meanwhile, in the above-described conventional controller driver, includes a display memory 121 for one frame, enclosed therein and, if the display picture is not switched, image data transfer from the image rendering device (CPU) 20 is halted to output image data stored in the display memory 121 to the display unit 30. The display memory 121 is enclosed with a view to reducing the power consumption, by transferring image data of only changed pixels from the image rendering device (CPU) 20, even when the display picture is changed over to a new picture.
Recently, video as well as TV functions are loaded on a mobile phone and chances of displaying moving images have increased in keeping with diversified functions of the mobile phone. Each frame is on the order of 60 Hz (16.7 msec). The response speed of a liquid crystal material is on the order of 20 to 30 msec for binary representation for white and black. For half tone representation, the response speed may occasionally exceed 100 msec.
FIG. 17 schematically shows a response example of a liquid crystal panel. FIG. 17 shows that the luminance response is delayed against changes in the applied voltage. There are occasions where the response time of several frames is taken until desired luminance is reached.
As a method for improving the response speed of the liquid crystal, there has so far been proposed driving according to a over-drive method (hereinafter referred to as “over-dive driving”). If, in this over-drive method, a change has occurred in a picture, as shown in FIG. 18, a voltage higher than the usual voltage is applied to a liquid crystal panel during rise time and, during fall time, a voltage lower than the usual voltage is applied thereto, such as to improve the response speed at the time of changes in the grayscale. Since the over-drive and the under-drive may be present together, depending on the direction of transition, the term ‘response time compensation (RTC) is sometimes used in place of the over-drive and the under-drive (for example, see Non-Patent Document 2, indicated hereinbelow).
FIG. 19 shows an illustrative configuration of effecting the over-drive driving (for example, see Non-Patent Document 1, indicated hereinbelow). Referring to FIG. 19, this liquid crystal panel apparatus includes a segment electrode drive circuit 204, an image memory 201 for storage of one frame of digital pictures for display, and a ROM (read-only memory) 202, also termed a lookup table, having stored therein a table for image data corresponding to two inputs of image data read out with a delay of one frame from the image memory 201. In case image data have changed, optimum image data, stored from the outset in the ROM 202, are read out, in dependence upon the magnitude and the direction of the change caused, to drive a liquid crystal panel to render the rise and the decay of the light transmittance acute within a necessary sufficient range. Meanwhile, a synchronization control circuit 203 supplies a write/readout signal for the image memory 201, while supplying a timing signal to a segment electrode drive circuit 204 and to a common electrode drive circuit 205.
There has also been known a configuration of a liquid crystal panel driving apparatus for effecting the over-drive driving, using a frame memory and a lookup table, in which part of input data and part of data of a previous frame from a frame memory are supplied as addresses to the lookup table and data for over-drive is generated based on output data of the lookup table and on a non-use part of the address of the input data, such as to reduce the memory volume of the lookup table as well as to reduce the step differences of over-drive data (see, for example, the Patent Document 2, indicated hereinbelow).
Patent Document 1
JP Patent Kokai Publication No. JP-A-4-365094 (FIG. 1)
Patent Document 2
JP Patent Kokai Publication No. JP-P2004-78129A (FIG. 1)
Non-Patent Document 1
μ PD161622 Data Sheet S15469JJV0DS [386 output TFT with enclosed RAM-Source Driver for output TFT-LCD], page 2, ULR <http://www.necel.com/nesdis/images/S15649JJ2VODS00.pdf>.
Non-Patent Document 2
Richard I. McCartney, 48.3: A Liquid Crystal Display Response Time Compensation Feature Integrated into an LCD Panel Timing Controller, SID 03 DIGEST